That is the point of the transformer.

I am assuming the OP has only a single circuit out to a shack in an outbuilding or such,  with the transformer at the shack he can make that two wire 240V circuit functionally provide 120-0-120 giving the ability to run both 120 and 240V equipment in the shack.

UK practise would have that underground cable overload protected (and probably earth leakage (RCBO) protected) at the supply end and would probably give it its own breaker.

Transformer sizing is not entirely obvious if you do the centre tap transformer thing to produce a centre tap on the split phase supply, but does allow a smaller transformer then doing an isolated step down would.

73, Dan.

I don't know how something like this would sit with the NEC, but could you not re use the existing 120V circuit as a 2 wire 240V line (no neutral) and then use a 120-0-120 transformer (or autotransformer) at the shack to recreate the neutral locally?

This would remove the need for pulling in new wire, and would simply require a two pole breaker at the supply end and a suitably rated transformer at the shack to create the local neutral.

Seems to me that a couple of KVA should probably suffice for the required transformer, which is not a huge deal.

73, Dan.

Well third harmonic is usually about 13dB or so down on the fundamental, so that would imply 5% power reflected by a simple LPF (At a KW. the reduced heat in the filter may be a bigger win then the reduced heat in the PA).

IMD is pretty much a suck it and see issue here as it could be better, could be worse depends on how things combine, and IMHO so many amps are so poor here anyway that there are much easier ways to make big improvements before worrying about reflected power.
Once you have the amp itself doing better then maybe -45dB ref PEP IMD3 then this sort of thing becomes worth worrying about, but with many SS amps not even managing to hit -30.....

Iff you have done everything else to build as clean a solid state amp as state of the art permits, then it may be worth it, but for something like an EB104 or such, I have my doubts.

73, Dan.

2012, and the article makes it look like it may have been in since 2010.

73 Dan.

I simulated it with 0.05 ohms as 4 * 0.2 ohm 1W 1812 packages (I make PD about 2.5W for each set of drain resistors), with solid ground plane on the back of the board and extensive vias for both thermal and ground impedance, and it appears to remain reliably stable.

Now granted LTSpice is not a proper RF spice package, and I may well have left out some of the in parasitics from the mosfet and transformer models, but the fact the version in the ARRL book apparently works leads me to think the idea is not unworkable.

The boring thing is that a lot of the more modern parts (Those freescale things) make this very difficult to do as they combine the source and thermal connections.

Time, methinks to do a board layout for my version, build it and see what happens.....

Regards, Dan.

It transpires that there is a design doing pretty much what I had in mind published in the ARRL Handbook, chapter 17 (The 250W SS amp they show).

I especially like the trick with dumping the second harmonic into a resistor via the power supply injection bifilar, going to have to borrow that. 

The other subtle trick in this design is the two separate transformers wound on a single pigs nose, used for both the output match and the SWR bridge, very nice idea.

250W from a pair of VRF151, IMD3 ~-38dB ref one tone (-44 ref PEP), so the degeneration obviously works, be interesting to see what the numbers are on topband (where the magnetics often become an issue).

73, Dan.

Hi all,

Has anyone got any experience with using source degeneration in high power mosfet power amplifiers?

It seems to me that 0.05 ohms or so in series with each source connection should help flatten the gain over frequency, raise the gate impedance a useful amount and significantly improve IMD figures at the cost of reducing the stage gain...

SPICE says yes,  but I have not seen it done in an amateur service power stage (I have a military power block that does it).

If I can get something like 10 - 13dB of gain with degeneration and feedback from two of the modern power fets, that would be sufficient for my needs, and with the local feedback should suffice to make the exciter the limiting factor for intermod (and possibly noise). 

Regards, Dan.

Seems to me that TAPR are quite open about the absence of warranty, so I really don't see where the beef is.

Number of layers is not all that important to ability to fix the thing actually.

DAC and PA are  SOIC or similar IIRC, so no real problem to replace them, most of the passives are 0603, so no real issue there, the AD and FPGA are the only things that look to be a serious ball ache to replace, and even they look like good candidates for chipquick or similar.

I still say there is nothing on there which would cause serious pain to replace if you had to, and most of the sand is readily available.

It actually looks more easily fixable then most of the boat anchor rigs I deal with, most of the parts being easier to source.

Regards, Dan.

Depends, most of the radio is in that FPGA, so if you are loading your own VHDL or verilog I would say that puts you into the experimenter category....
There is no clear cut line between experimenter and black box operator.

I for example do not blow my own vacuum fets, and have been known to buy modules from minicircuits upon occasion, which makes me more of an appliance operator then those who make their own tubes (There are a few out there), but I would say that deciding to buy in the hardware if your interest is in the HDL design of a rig is quite reasonable.

Hell, I know folks doing serious experimental work where the entire RF chain is off the shelf black boxes, doesn't make it appliance  operation.

73 Dan.

I just bought an Altera Cyclone III dev board, which is actually some very cool hardware when hacking on the VHDL for SDRs.

Plan is 16 bit @ 200Mhz sample rate for both TX and RX, with the ADC used on TX to close the loop around the amplifiers, the only slight pain is that the ADC part falls under ITAR restrictions in the US for some reason, so some paperwork will be required to get it into my hands (That, and it is a £100 chip). 

Regards, Dan.

I don't see anything that small on there (0603 passives from the look of it), given a decent hot air tool, some chipquick and solder wick, it all looks eminently fixable to me.
Not convinced about the fast opamps as PA thing, but it obviously works well enough.
6 Layers seems overkill, 4 feels like it should be doable.

Actually the thing looks like nothing so much as a slightly tarted up version of the HiQSDR architecture from N2ADR and friends, which I am playing with for a slightly different purpose (Putting the RX ADC to use on transmit to close the loop).
Given the number of golden screwdriver types out there, I would really not want to sell a set of bare boards with a promise of much handholding for something like this.
If a few expensive paperweights happen in a group which pretty much by definition are not exactly end users (at least not of the appliance operator type), and where it is plenty obvious what people are getting into, where is the harm?
But there is also a distinct lack of insulting notices like "No user serviceable parts inside", this stuff is IMHO being marketed to the sort of people who view that kind of thing as a challenge, not to end users who want a black box with support.
The target market for this thing is both RF savvy, and knows its way around digital logic and high speed PCBs, most breakages will just result in a order to farnell/mouser/digikey for whatever has broken.

Would FLEX do much better support wise if you took a rig back to them having broken it while experimenting with your own custom FPGA load?
Does ANYONE sell a bare board PA strip (No output filters, no VSWR foldback) with a warranty? I would be very surprised, these are modules for experimenters of a fairly advanced sort, not black boxes.
I can think of another SDR where some have said much the same thing!

Now I am not using the TAPR boards, preferring to do slightly my own thing, but if you want to live on the bleeding edge then you really have to be able to provide your own support sometimes.

73, Dan (Ex 2E0CHE, now M0HCN)

Hi all,

I am currently playing with the design of a DUC/DDC HF rig using an architecture not a million miles from HiQSDR (With a few twists), and the thought occurred that I don't see any dithering of the word length reductions in the verilog code for the FPGA in the existing code.

This might very easily explain some of the non harmonic spurs on transmit as well as possibly some noise on receive.

Now, TPD dither is easy to implement, but I am wondering about simple minded noise shaping, if the dither can be shaped to put most of the noise power above the 6M band, then it can be filtered out and the transmit noise floor will improve.

Has anyone here got any experience with designing noise shaped dithering code for very high sample rate applications (well over 100Mhz data rates (Potentially 200Mhz or so), so multipliers are expensive, I am thinking CIC highpass filters). 

My overall plan is to use the RX ADC on transmit to close the loop with all the cartesian feedback being implemented in the FPGA at a few hundred Khz or so sample rate.
This would allow a cartesian loop transmitter to be implemented without needing meaningful numbers of extra parts over those required for a open loop PA (The nice thing about FPGAs is that even hardware is "just a small matter of software").
 
Regards, Dan.

Yea, SPI and I2C tools I have, hooking it to a computer to configure the thing is not a major concern.

I am probably going to go with an AD9910 DDS or similar for the LO generators, with the reference clock divided down to clock the I & Q dacs so everything is locked to the same master reference.

Regards, Dan.

I looked at the 998, but could not locate a source in sane quantities, none of the usual suspects carry the thing that I can see, and distributors usually want to sell me a compete reel.

Note that you will need a micro and some DACs to trim out the DC offsets on the I & Q inputs.

I went for a pair of H mode quadrature mixers driven by two DDS chips to make a 9Mhz first IF, then mix up to (and down from) 85Mhz, before a final mixer pair produces the HF output. 

An interesting thought is that the 5585 and its companion modulator could be used, with a second modulator used to produce the variable phase shift needed to allow the loop to be closed by simply applying DC levels to the I & Q inputs to set the phase of the generated output.

Broadband noise is a concern, particularly as I am trying a HF set, rather then a VHF one.

Regards, Dan.

The first part of the problem can be trivially addressed in a DSP based exciter by noting that the envelope of any modulation scheme is trivially bounded by sqrt (I^2 + Q^2) at baseband.

Here is a band limited square wave (The pathological case for SSB):
http://www.exponent.myzen.co.uk/Bandlimited square wave.png 
Here is the calculated envelope by this method http://www.exponent.myzen.co.uk/Baseband_I_Q_Mag.png
And here is the calculated RF signal plotted on the same plot as the above calculated envelope:
http://www.exponent.myzen.co.uk/SSB_RF_Baseband_envelope.png

Thus a limiter operating in the DSP on |Z| where Z is the analytic pair will suffice to limit the eventual RF output at any desired level.

There does need to be a feedback path returning at least VSWR, or more usefully a sample of peak drain voltage and current to the modulation DSP so it can adjust the limiter threshold level to keep the PA in safe operation, but extending this to an external amp while not particularly tough is not something the market expects (A power sampler head cabled back to the exciter).

There is also a potential issue with tube amplifiers here in that they can quite happily match into loads quite a long way from 50 ohms, where the power sampler would probably assume a 50 ohm match.

The takeaway from this is that if ALC is employed, the external amplifier should have as much ALC bandwidth as possible, so as to have minimum effect on the loop dynamics implemented by the exciter, certainly the ALC output should have a bandwidth at least or the same order as the modulation bandwidth.

Better would be for the amplifiers to provide a sample of the internal directional coupler output at a standard level on a pair of BNC or similar, if everything provided samples at say 0dBm = full rated power (or maximum rated reflected power), then the rig could use these samples to actually close the loop in a sane way with more or less fully known loop dynamics. 

73, Dan (Who is designing a homebrew radio using these methods, hence having the plots available from my development simulations).