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[2E0ILY]

OK, it;s not actually a SMPS, but similar, a 136kW LF amp. I built it some time ago.

Having suffered with blown FET's on a 1kW 136khz Class D amplifier since doing some circuit mods I realized the limitations of my novice status and did some Googling. I had been looking at gate and drain wave forms and saw nothing horrible to my eyes. I then read up on "dead time" the time neither device should be on to stop short circuits or over current, using two channels and two probes. This gives the waveform attached (I hope...) and to me there doesn't seem to be any real dead time. Is it my measurement inabilities, my misunderstanding of dead time concepts, or have I found an issue? The amp usually uses two paralleled FET's per "side", to minimize cost in blown FET's I have been running just one per side. Even on reduced voltage to the PA FET's I get one popping quite often, and I can see no other issues, like bad antenna matching etcetera.

Where does "dead time" come from? Is it from the architecture of the driver chips(s) itself / themselves? Or is external circuitry needed? I see propagation delay figures cited, but I don't think this is the same as dead time. The fact I see no dead time figures stated for either of these IC's makes me wonder how it is created...

I put the red and blue cursors on where I expected to see the dead time, but the switching looks instant, maybe I am not running the scope fast enough? On the drain waveform capture I am not sure what the blip is before the drain voltage rises. Is that some dead time, or an attempt for both devices to conduct together?

I changed from a single dual output inverting gate driver chip type TC4426 to two single output inverting chips type TC4452 in order to be able to drive more powerful, higher gate capacitance MOSFET's in the future. Maybe these have caused an issue, I had nothing like the same failure rate before my mods.


I attach links to their data sheets and the amp's schematic. Thanks.

Basic schematic showing original single, dual output driver IC, which seemed to be far kinder on FET's

http://www.gatesgarth.com/136bigv2mods-8.jpg

Gate driver signal capture at gates of the PA FET's, just running a pair at 50V:

http://www.gatesgarth.com/no-dead-time.jpg


Drain pins captures:


http://www.gatesgarth.com/drain-no-dead-time3.jpg


Original dual output driver IC specs:

http://www.gatesgarth.com/TC4426.pdf


New dual driver chips, each with just a single output, much higher current and gate capacitance ability:

http://www.gatesgarth.com/TC4452.pdf


Thanks for looking!

[W9IQ]

Chris,

The MOSFETs turn on about six times faster than they turn off. Without a detailed analysis of the original circuit vs your modified version, my first guess would be that the changes you made disturbed the timing that was inherent in the original circuit and you now have the MOSFETs briefly cross conducting.

The "dead time" is a timing issue that is a combination of the driving chip and the MOSFET gate capacitance. You could also enforce a gate timing constraint through logic to ensure they don't cross conduct. About 150 nS or so is all that is probably required.

- Glenn W9IQ

[KH6AQ]

The waveform labeled ...time3 appears to show about 800ns of cross-conduction. This can be seen as the small spike upward in the upper waveform that coincides with the falling lower waveform. Note that the duty cycle is not 50%.

The solution is not the use of higher current gate drivers, although that might be needed for efficiency (less time in the linear region), but to add some actual dead time.

There are many ways to do this. One way is to add a diode and capacitor between the 4013 and the TC4426. The 1k ohm is changed to 10k ohm. The diode (1N4148 or similar) is placed across the 10k ohm resistor with its cathode toward the 4013. A 150pF capacitor is placed from the TC4426 input to GND. This delays the ON command by about 1000ns, slows the OFF command by perhaps 100ns, and provides 900ns of dead time.

The drawback to this circuit is that because of component tolerances the ON time of each MOSFET could be slightly different (perhaps 100-200ns) and the output transformer may saturate. One way to reduce the timing difference is to use 1% resistors and 1% capacitors. If you don't have 1% capacitors you can measure a number of NPO ceramic capacitors and chose two that are very close in capacitance. The R and C values can be adjusted to use what you already have.

Another way to introduce dead time is to replace the 4013 with a 4017 and change the 272 kHz signal to 1360 kHz. The 4017 outputs are ORed using 4-input XOR gates or with diodes. 4017 outputs 0, 1, 2, and 3 drive one TC4426 input while outputs 5, 6, 7, 8 drive the other TC4426 input. The 4, and 10 outputs do not drive and they provide dead time. The dead time is 735ns. This is barely enough time dead but with the stronger gate drivers, and changing the MOSFET gate resistors to 2.2 or 3.3 ohms, there should be no cross-conduction.

Check my math and logic on this.

[KH6AQ]

I should add that I have used both of the circuits I describe to add dead, or OFF, time to driving two MOSFETs.

[AB3TH]

You have a bit less than a microsecond when both FETs are simultaneously on.  Each FET is on for about 4.5 microseconds.  They should alternately be turned on for a maximum of 3.6 microseconds.  This isn't a totem-pole circuit where both upper and lower switches being on would cause destructive current.  It's a half-wave circuit.  Both FETS being on will cause common-mode current in the transformer.  At the least this will reduce your efficiency a great deal.  You don't need a lot of dead time but now you have overlap.

Your circuit mod keys the transmitter by turning off power to the flip-flop and the driver.  This is not good.  Without power to the driver the gate drive decays slowly through the gate resistor rather than being driven low by the driver.  So, when the keying turns off you have no idea what's going on.  You might be getting high voltage spikes on the drain.  You should have a pair of 'and' or 'nand' gates following the flip-flop so the keying turns off the inputs to the driver and both FETS get turned off quickly by the driver.  Making the gate 3-input allows you to add a delay off the clock and 'and' that with output of the flip-flop to get zero or positive dead-time rather than overlap.

[2E0ILY]

Some excellent info as always on this forum, thanks to you both. The 12V is on all the time, the MOSFET that looks like it's for keying is now redundant. I just start and stop the 2X frequency drive for a WSPR or OPERA session. I added 470nF caps between the driver and PA MOSFETS so if the no drive protection circuit fails they still can't see DC from the 4013 if it locks in one state. That part of it doesn't seem to have caused any issues. Do you think the amount of time both are sort of on would be destructive? it seems pretty reliable at 50V, biut on it's full whack of 100V it is no longer anything like as reliable as it was with the dual output TC4426 driver chip. Unfortunately I don't have scope captures from when I used that IC.

Thanks again, most helpful stuff!

[W9IQ]

You may also wish to consider adding high power TVS diodes across each DS. Often driving an inductive load will exceed the DS voltage rating. As you increase voltage, the potential for this failure mode obviously becomes more pronounced.

- Glenn W9IQ

[2E0ILY]

Right, I think I finally may have a handle on this and it could be transients. When a transmission starts I never seem to have a failure that I can recall. It's when a transmission ends. The amp has 12V and 50 or 100V permanently on. The transmission is solely instigated and ended by starting and stopping the drive signal. When I scope the drain to source pins with a proper pigtail as the ground on my probe, set to X1 but with a X20 attenuator I use for automotive work, I see these captures. A TX starts nicely. A ceasing of a TX, even into a Bird 400W dummy load often shows one or more transients up to 770V in the worse cases, well over the FET's rated drain to source voltage limits. Sometimes one pulse, sometimes three or more over about a 70uS time frame. I can only show part of the capture of course. Bear in mind the voltage axis figures need multiplying by X 20!

Am I right thinking this could kill a FET? Would a TVS diode be happy across a drain / source running at 136kHz? Would it be fast enough to catch such pulses? Is there another way to quell the pulses? Thanks!! First image is the start of a TX session using WSPR. Second image is the drin / source capture when the same transmission ends.
 

[N3QE]

Am I right thinking this could kill a FET? Would a TVS diode be happy across a drain / source running at 136kHz? Would it be fast enough to catch such pulses? Is there another way to quell the pulses?

A TVS can certainly be part of a snubber.

What has happened is that while the the MOSFET is driving, it has low impedance every cycle. But now you've stopped applying drive and the MOSFET is high impedance and you need a snubber to stop voltages from rising to high levels.

As a rough guide, if you wanted to think of a Zener or TVS in series with a R that is a few times bigger than the MOSFET design impedance, that is often good enough at very low frequencies. At the middle ground where you are at, a RCD or R2CD snubber network may be more suitable. In a previous field I used to work in we always called the C in parallel with the R, the "speedup capacitor", I'm not sure if that's quite right for a SMPS snubber but it's one way to think about it.

[AB3TH]

This is a good example of why you want to use Spice to model the circuit.  It's simple enough.  This may save replacing parts at random when they blow up.  Your transformer will be a problem to model realistically but you can get a general idea.  The resonating caps on the transformer may need to be adjusted.  The SWR of your antenna will have a big effect on the transient as will the turn on/off speed of the FETs.  You might need better matching.  Rather than just driving the FETS with a squarewave at half the frequency you might want an actual PWM sinewave drive.  If you do a Spice model you can play with things and see what it does.  LTspice and Tina are free.

[KH6AQ]

Can you describe CH1? What is the inductance?

[2E0ILY]

AB3TH, thanks for the idea, but I am not at all sure I am ready for SPICE, but with all honesty I haven't tried to use it, so  I ought to give it a go, and I will.

N3QE, thankss that's helpful, too and appreciated.

WX7G  I have uploaded the original schematic and build documents to my server, bear in mind I was running off a regulated 100V supply with pretty good reliabilty until I rebuilt it to gain better FET access and add better fault indication and a different over current transducer. The choke CH1 is 20 turns of 12g enamelled wire on a half inch ferrite rod, close wound. it measures at 20uH. The designer did it like that so he could put a Hall effect transistor looking at one end of the rod for over current sensing. I have tried a toroidal choke with a T157-26 core (1.57 inch OD) with 25 turns of 14g enameled wire, and measuring about 59uH. My scope sees a lot less RF on the power supply side of it than with the ferrite rod, but the voltage spikes at the end of a TX session remain unchanged. W1VD made this comment on a LF forum:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

"Chris
 
I had a similar problem years ago ... only with WSPR ... an occasional FET failure only at the end of transmission period. It was traced to momentary cross conduction generated spikes. The solution was to add dead time between the phases. See C1 and C2 plus the 15k resistors in between the flip flop and the IR2110 ... schematic at http://www.w1vd.com/137-500-KWTX.html . Don't think you're using the IR2110 driver ... this device has internal 'safeguards' that may not be in other drivers. Suggest you compare data sheets. B+ runs continuous in this amplifier.
 
As usual ... caution when marrying together circuit ideas from different sources ... unexpected results may occur.
 
Jay W1VD  WD2XNS  WE2XGR/2   "


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I haven't tried this yet as I have run out of damned FET's. I should also mention I am using more robust FET's these days, they are specced here:

http://docs-europe.electrocomponents.com/webdocs/1468/0900766b81468028.pdf

Thanks for your continued help and interest in this.

[N3QE]

solution was to add dead time between the phases. See C1 and C2 plus the 15k resistors in between the flip flop and the IR2110 ... schematic at http://www.w1vd.com/137-500-KWTX.html

2E0ILY - it's a different feature that what's being pointed out above - but see in particular R1/C3 and R2/C4 on W1VD's schematic. That's a simple RC snubber.

The nominal DC current drain of W1VD's RF deck must be more than 20Amps at 50V. So estimate a nominal closed-state source impedance of an ohm or so. R1 and R2 are 10 ohms, 10 times bigger than 1 ohm, so are kind of in the wash compared to active drive levels. But when drive dissapears and the MOSFETs go open circuit, R1 and R2 are what absorb any energy left in the tank before the voltages get high enough to damage the MOSFETs.