Using ECL Logic

[TANAKASAN]

I'm not sure if this should appear in the Homebrew section or Computers but I'll try here first. I'm looking for someone who has experience in using ECL logic, specifically PECL chips.

1) If I am connecting PECL output to PECL input does every connection need a terminator? The reason I ask this is that on a small project using PECL this would mean about twenty terminators and this seems unreasonable.

2) If I connect a single PECL output to three PECL inputs then do I use three terminators or one?

3) Standard termination method is a 50 ohm resistor from the line to Vcc-2V. If I terminate each output to ground and use a slightly higher resistor value would this still work or would the logic levels be wrong?

4) Finally, can someone recommend a chip that will convert an 8-bit PECL output to 3.3v CMOS levels? Speed will be low, about 10 MHz.

Thanks in advance.

Tanakasan

[N3QE]

1) In modern usage the PECL terminators would be tiny resistor networks.
1a) If the PECL signals are fairly static slow data these may not have to be terminated on a short on-board run. But that leads to the question, why did you convert them to PECL in the first place if they are slow unclocked data?
1b) If the PECL signals are clocks or latch enables etc. you probably want to terminate them.
1c) By Thevenin's Theorem most usual way to terminate PECL will end up being like figure 4  in http://www.micrel.com/_PDF/HBW/App-Notes/termination.pdf

2) One terminator at far end. But it is unusual (see my note below 4) to fan out PECL. If necessary to split a signal multiple ways there are fanout buffers e.g. SY100EP11U, but this would be an unusual use of PECL.

3) Wrong. But note by Thevenin's theorem, a 50 ohm resistor to Vcc-2V, can be replaced by two resistors one to ground and one to Vcc. See 1c above.

4) http://www.onsemi.com/pub_link/Collateral/MC100EPT622-D.PDF

Overall note: Today you are most likely to see PECL or LVDS used on board-to-board or assembly-to-assembly interconnect cables. It'll be translated to whatever's used on the board right at the terminator.

[TANAKASAN]

Thanks for the reply, some additional information.

The board will be a prescaler operating at about 2 GHz. Whilst the inputs will be operating at this frequency the divided outputs will be at about 10 MHz after being divided by 200 (C8 Hex).

The reason for asking about fanout is that at one point the counter logic has one output driving three inputs, I wasn't sure how this should be handled.

I have some ECL chips on order, now may be the best time to experiment.

Tanakasan

[N3QE]

Thanks for the reply, some additional information.

The board will be a prescaler operating at about 2 GHz. Whilst the inputs will be operating at this frequency the divided outputs will be at about 10 MHz after being divided by 200 (C8 Hex).

The reason for asking about fanout is that at one point the counter logic has one output driving three inputs, I wasn't sure how this should be handled.

I'm guessing your divide-by-200 is PECL in PECL out.

If you want to split the divider's output 3 ways and especially if they are going off-board and small skews is important, a SY100EP11U or MC100LVE310 type device is your answer.

Again PECL and LVDS are wonderful if you have to drive another board over a short distance twisted pair etc. But on board... look at your skew budget and you may well find that TTL levels will do fine at 10MHz.