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Author Topic: Flex Site: "Imagine a transceiver that changes Ham Radio - Forever.."  (Read 48761 times)
KE5JPP
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« Reply #75 on: June 11, 2012, 03:52:30 AM »

VE3WGO, here is an example to help you understand your erroneous thinking.

Let's say I take a high speed 16 bit ADC and run it at 100 MSPS.  The spec sheet shows it has a noise floor of -75 dBfs (dB below full scale) @ 100 MSPS.  I use a clean low phase noise 100 MHz clock to clock the ADC.   We have a FPGA connected to the 16 bit ADC's bus and the speed of the FPGA is sufficient that it can be clocked at 100 MHz like the ADC.  In the FPGA we have RAM that can store a block of continuous 16 bit samples from the ADC.  The ADC has a full scale (clipping) limit of 0 dBm (which is about S9+80).  After capturing a block of 16 bit samples from the ADC into the RAM in the FPGA, we transfer the block of samples to a PC where we do a FFT on it.  We find that the noise floor is about -75 dBm and signals below that cannot be resolved (without filtering).  The noise floor is NOT -90 dBm or so as you would expect by your estimation of the ADC's 90 dB or so dynamic range.  That is because high speed 16 bit ADCs currently on the market has ENOBs (effective number of bits) in the 12 to 13 bit range, thus the noise floor rating of -75 dBfs (dB below full scale).  The current 16 bit ADCs are coming up against limits imposed by physics and will not improve very much in the future.  (Of course, you could immerse your ADC into liquid nitrogen to improve this somewhat).  So the bottom line in this case is that at 100 MSPS, your upper limit is S9+80 and your lower limit sensitivity is about S9.

Now, using the same ADC and FPGA arrangement above, let's decimate and filter the samples so that we decrease the sample rate to 100 kSPS from the 100 MSPS rate (a decimation of 1000).  Let's store the samples in the FPGA RAM as before, but because of bit growth in our filters, we must now store the samples as 24 bit samples, not 16 bit samples.  We transfer a block of those 24 bit samples to our PC and do a FFT on it.  We now find that the noise floor is now about -104 dBm.  That is significantly better than the 90 dB or so dynamic range that a 16 bit ADC would indicate!  Our upper limit is still 0 dBm or S9+80, but our bottom limit to sensitivity is now around -104 dBm or around S4.  This is the result of decimation and filtering (bandwidth reduction).  Because of our decimation by 1000 we have gained 27 dB in dynamic range by the formula process gain = 10 * log10( 100MSPS/ 2 * 100kSPS) = 26.99 dB.  So the -75 dBFs of our 16 bit ADC is decreased to -(75 + 27) = -104 dBfs.  Process gain comes from the fact that the noise in the 100 MSPS ADC is spread out over the whole Fs/2 bandwidth and when we decimate/filter we bandwidth limit that noise to some smaller bandwidth (100 kSPS/2 in this example).  Decimation of more than 1000 will decrease our noise floor and sensitivity even further.  Run the numbers for a 500 Hz bandwidth and see.

That is how modern direct sampling SDRs that use 14 and 16 bit high speed ADCs are able to achieve much more dynamic range than what 14 or 16 bits would indicate taking your simplistic understanding of digital signal processing.

Anyone that actually owns a SDR, such as the Flex-5000, can see this real effect in the spectrum display.  In PowerSDR, for example, switching between sample rates of 48, 96, and 192 kHz causes the noise floor to increase in the panadapter as you increase the sampling rate.  Also, in PowerSDR, when the filters are narrowed from 3 kHz to 500 Hz, you can see that the indicated noise floor on the PowerSDR S meter decrease.  The S meter in PowerSDR shows the power within the filter, where the panadapter in spectrum view shows the power (actually power spectrum) before the filter.  That is why they are different.

Gene
« Last Edit: June 11, 2012, 04:01:38 AM by KE5JPP » Logged
KE5JPP
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« Reply #76 on: June 11, 2012, 05:11:58 AM »

Typo warning: -75 dBfs should have been -77 dBfs above, but the idea is still the same.

Gene
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